Big Iron Secrets

Underpinning it all, the not so humble CPU does a big job. Unfortunately, in many situations, our standard cores aren’t up to the task. Not enough cores, not enough cache and not nearly enough throughput capability make standard CPUs lacklustre in the high performance environment. So we look to alternative architectures, such as SPARC, IA-64, and IBM Power6. We’ll not mention Cell here, as it is a base derivative of the Power architecture.

SPARC
Whenever you log into your bank account or download pictures of your Guitar Hero-obsessed JB-Hi Fi employee mates, you’ll likely be hitting a Sun backend. On recent Scalable Processor Architecture (SPARC) systems, such as the T1000, T2000 or Rock hardware, you’ll not just find four CPU sockets, but on each CPU, 16 hardware threads of execution. In a four-socket system, you’ve got 64 hardware threads to scorch the client load with. Of course, with all these threads to play with, you need a system bus many, many times greater than what is traditionally offered in the x86 world. The Sun M9000 series SPARC-based enterprise system has a maximum attainable backplane throughput speed of around 368GB/sec or 1.032 TeraFLOPS (floating point operations per second). No. You’re PCI-E 2.0 bus can’t do this. It is a mere toy.

Sun M9000 series Enterprise Computing Structure

Figure 2 shows Sun’s CPU technology in action. Many CPU cores associated with transactional cache and quad connected memory controllers, all communicating through a crossbar interconnect. This crossbar is the secret of Sun’s ability to do dynamic reconfiguration of resources. Because of this crossbar, the enterprise backplanes are capable of something a little quirky. One can dynamically add pools of CPUs, cores and system resources to different hardware domains (often called LDOMs, or logical domains).

The Sun SPARC 'Rock' Architecture

An example of LDOM resource groups is where large financial database systems find themselves in a situation where user load becomes too large for the current logical domain to contend with. No problems. Simply tell the domain you’ll add another CPU to the processor pool. Equally, if DIMM’s (dual in-line memory modules) fail mid-flight, it is of little consequence. You can turn off individual banks or slots on a per-DIMM basis – and swap it out hot.

IA-64
Intel’s IA-64 architecture started life as an initiative to create high performance 64-bit computing. IA-64 (Itanium) was not a 32-bit CPU with 64-bit extensions, but a total reinvention of bus, register location and cache methodology (L1, L2, and L3 being on die up to 16MB per cache level). Intel aimed this CPU at HPC, along the lines of the SGI Altix series.

The downside was that the IA-64 architecture was hard to compile for, and the platform failed in terms of sales figures. Several years later, Intel created the Itanium 2. The new IA-64 supported higher FSB, better 32-bit legacy support and far more flexible socket connections. Intel broke the high-end server market at this point, and the IA-64 became a commonplace processor in the mission critical server market.

The 9000 series 90nm Montecito provides an eight-stage pipeline, running at 1.66 GHz. This consists of six integer units, six multimedia units, two load and two store units, three branch units, two extended-precision floating-point units, and one additional single-precision floating-point unit per core. The hardware employs dynamic prefetch, branch prediction, a register scoreboard, and non-blocking caches. Three levels of on-die cache (count all that cache in the architecture diagram!) minimises overall memory latency.

Intel IA-64 Itanium 9000 Architecture

The astute reader may have noticed the one thing the Itanium 9000 shares in common with our current Core2 architecture CPUs – a register scoreboard. You may have also noticed, if you’ve looked deeper into it, that the 9000 series CPU employs software pipeline technology. Think of it like HyperThreading with less cache misses.

The SGI Altix 4700, at NASA

Power6
The IBM Power6 architecture is a competitor to Sun’s UltraSPARC IV+/IX series of CPUs. The Power6 is the fastest in-production-stock processor, clocking from factory at 4.7GHz on a 65nm fabrication. Each core has multiple integer units; two floating-point units and all cores in dual core packages are capable of SMT. Where Power6 becomes entirely unique is the treatment of arithmetic units.

Rather than having floating point units hanging off the side of cache and the central processing logic, the Power6 uses dedicated decimal logic units. The architecture shines in extreme floating point operationally intensive tasks. This is a result of the 50 additional floating-point operation instructions not present in x86-, IA-64- or SPARC-based architectures. IBM has the edge on raw floating-point flexibility. From the architecture layout, we can see additional memory logic in the form of a 32MB cache controller.

IBM's Power6 architecture

No matter how the enterprise CPU vendors construe it with their changing arithmetic units, different cache technologies and their varying threading models, the world is moving away from plain symmetric multiprocessing and is moving towards chip multithreading (CMT), allowing single CPU fabrications to utilise many hardware threads per physical unit, going a step beyond the taxonomy of simply adding more cores for more power. Not only do we add cores, we add multiples of threads every time we add a core.