Performance growth - what are the limits? - Head to Head #28

Dr Carlo Kopp offers a more intimate examination of the performance growth curve to show you what you're missing out on.

Over time, performance growth, and its corresponding reductions in dollars per performance, show an unbroken growth curve since the 1960s. There have been the occasional peaks and dips, but largely the Moore's Law curve has remained an unchanging feature of life in the computing game.

Moore's Law has sadly become a bit clichéd, after being quoted by all and sundry to support arguments that often have no substance. Marketers too often believe that mentioning the magic two words somehow confers credibility to the incredible.

In this month's discussion we will look a little more closely at the factors underpinning Moore's Law, and the broader issue of performance growth limits.

Most readers will have a keen appreciation of the reality that modern CPUs, GPUs and support chips are fabricated (fabbed) on wafers of very pure Silicon. The complex circuitry which makes up a modern processor or support chip is the result of repeated photolithography, etch, diffusion and polishing operations performed on the wafer. A microprocessor for instance is a very complex collection of logic circuits, each made of gates and latches - the gates and latches in turn being made up of individual transistors. A modern processor has tens or even hundreds of millions of transistors on it, interconnected cleverly enough to form the CPU, GPU or support chip of choice.

Chip performance growth limits
What are the key factors determining chip performance growth limits, and how are they related?

The first factor is the architecture of the chip itself, or the manner in which its logic circuitry is interconnected. Architecture is a complex area: it determines why for instance a Pentium 4 and Athlon XP fabricated with identical transistor performance, and similar transistor counts, perform differently on similar tasks. Or indeed, why SPARC, MIPS and Intel architecture chips with similar transistor performance and counts often behave very differently.

Architecture can't be explained in two paragraphs -- it's too complex. Today's desktop PC is architecturally most akin to a 1960s or early 1970s mainframe computer. What can be said in two paragraphs is that more transistors on a chip permit the design of more sophisticated architectural features, which improve performance. Pipeline depths, numbers of superscalar or VLIW execution units, superscalar logic for detecting parallelism, branch target caches, instruction and data caches are all features which are feasible with millions of transistors on a chip. The larger and more complex they can be, the more they can deliver in terms of performance growth.

Dense and denser
If a computer architect can fit a larger number of transistors on a chip, then the architecture can be more refined -- the simplest analogy is the difference between a large 1960s fridge-sized minicomputer, and a three room-sized mainframe of that era. Both were built from chips of similar density, the mainframe delivering many times the performance because its architecture was more complex and able to do more things at once. The punch line is simple: the smaller the transistor size, the higher the chip density -- the higher the density, the more sophisticated the architecture.

This of course brings us to the heart of the matter: the humble little transistor. A transistor is a tiny, solid-state high-speed switch in a digital circuit. Since the 1950s we have seen a great many transistor styles appear, blossom and disappear. There is little resemblance electrically or physically between the Germanium alloyed PNP bipolar transistors at the cutting edge in 1955, the epitaxial planar NPN bipolar transistors in 1980, and the Complementary Metal Oxide Semiconductor (CMOS) transistors in today's Athlon XP or Pentium 4.

From an architectural perspective, the maxim for transistors is: the smaller the better, because we'll have more of them to play with. The payoff for shrinking a transistor is more speed. The smaller the transistor, the less electrical charge it needs pumped into it to make it switch, and typically the faster it can be made to switch. In many modern transistors the mobility of the charge itself through the semiconductor material, be it Silicon or Gallium Arsenide, becomes a limiting factor in how fast the transistor can switch. Silicon transistors start to run out of puff at several gigahertz, and the fastest current transistors in the market are Gallium Arsenide used in radars and satellite communications.

Will Moore's Law be broken?
Much of the Moore's Law argument in science circles centres on how small, and thus how fast, transistors can be made. Many transistor designs today are approaching the limits of the technology. Quantum tunnelling effects can cause them to leak charge and not switch properly if sizes are made dramatically smaller than currently. Another speed limiting factor has been the electrical behaviour of the insulating layers on the chip. Carbon doped Silicone dioxide and polymer materials are the current fix -- the traditional Silicon dioxide insulator forces transistors to pump more charge into the on-chip wiring to achieve a higher clock speed, thus wasting energy.

Size and speed have other effects. Power dissipation is one of them. Historically power dissipation has always been related to speed, and driving any transistor faster than its peers would make it run hotter. The shift during the 1990s to CMOS, then hardly the fastest transistor in the marketplace, was due to its low heat dissipation per switching cycle. Even so, today we see the nuisance of fan driven heatsinks on every larger chip.

CMOS transistors are uniquely good in this respect, as most of the waste power they release is produced during the switching cycle itself -- indeed in CMOS CPUs power dissipation (waste heat) grows mostly with clock speed. The rule of thumb is 'double the speed, double the waste heat'.

Getting rid of heat in a slab of Silicon is a perverse problem. If the thermal conductivity of the chip and package is too high, the operating temperature will rise, thus increasing the operating stress of the chip. Push it beyond some temperature and it will breakdown and convert itself into a pool of molten Silicon slag. Even below such temperatures, running hot impairs reliability. Density matters in this game. If we double the number of transistors, we double the total power to be dissipated, so for a given heatsink, this doubles the difference in temperature between the chip die and outside ambient. If we clock the chip twice as fast, dissipation resulting from transistors clocked faster will roughly double, with a similar effect.

In short: performance growth is limited by transistor and on-chip circuit speed, in turn limited by materials and transistor size, but also limited by heat dissipation and architectural design. There should be a law for it.