Is the G5 a rotten apple? We sent Dr Carlo Kopp to the orchid to find out.
The recent announcement of Apple's PowerMac G5, built around an IBM 970 microprocessor, puts Apple in the spotlight with a product that is highly competitive against the latest Intel and AMD offerings. In this month's feature we will explore the technology behind the G5 and make some comparisons against the Intel architecture world.
In the Beginning. . .In historical terms, the PowerPC architecture is about half the age of the Intel x86 architecture. The earliest origins of this product line fall into the late 1980s, the era of the Intel 486 and the dominance of Sun Microsystems in the Unix workstation market. This was a period when Intel architecture PC represented well and truly the `bottom end' of the market, both in price and performance. A top end Intel motherboard of that period would boast a 66MHz CPU chip, external cache, several ISA slots, but may have still used an ST-506 disk interface. A 100 Megabyte hard disk was worth many hundreds of dollars and the only Unix ports for a PC were the early SCO offering and the Interactive Systems port, later to morph into Solaris 2 for Intel.
The top end of the desktop market was an ongoing bloodbath between Sun Microsystems, Silicon Graphics Inc, Hewlett Packard, Digital Equipment Corporation (now Compaq) and IBM. Sun transitioned to their SPARC RISC architecture, abandoning the Motorola 68KB series, HP were developing the HP-PA RISC architecture, DEC were transitioning from the MIPS RISC architecture to the 64-bit RISC Alpha, while SGI drove the MIPS line harder and faster. IBM saw a major opportunity in the Unix workstation and server market, but had no product which could compete against the `RISC revolution' sweeping the workstation marketplace. IBM needed a product which could compete in SPECMarks performance against the top end of technology marketplace, and needed it badly in a world where the large mainframe market had saturated and increasing numbers of users were bailing out to buy larger Unix servers.
Thus was born the IBM POWER architecture. Performance Optimisation With Enhanced RISC - POWER - was the marketing label attached to IBM's then new RISC architecture. RISC architectures - Reduced Instruction Set Code - were a Berkeley idea from the early nineties intended to solve many of the performance and architectural problems of the then incumbent CISC - Complex Instruction Set Code - architectures of which the Intel x86 was a typical example. The typical CISC architecture of the era had a small number of registers, usually over two hundred instruction types, and used a microcoded control unit to drive the inner workings of the processor. Machine architects of the period observed that there were often never enough registers to go around, only 20% to 30% of the instruction types were being used by compilers, and the microcode in the CPU control units was an incessant source of pain. Why not make architectures with lots of registers, a small number of simple but fast instructions, and architect a simple hardwired control unit which can execute an instruction in one or two clock cycles rather than 6 or 10 as incumbent microcoded systems did? The RISC architectures emerging during this period observed the RISC religion with varying degrees of conformity.
IBM's first generation of 32-bit POWER Architecture chipsets started shipping in RISC System / 6000 or RS/6000 workstations during 1990 - the marketing label `RS' being the source of much mirth in the Australian market. This author had the pleasure of evaluating one in 1992, including a complete stripdown to board level, a rare treat for a SPARC designer of the period. IBM's RS/6000 was blitzing the SPECMarks and we all wanted to know how they did it.
What IBM had done was throw out the period convention of a RISC CPU on 2 or 3 chips, and an A4 sized or smaller motherboard. The first generation POWER chipset used either 7 or 9 chips in large chip carriers - the `CPU complex' itself occupying as much area as a whole SPARCStation 1 or 2 motherboard, and the motherboard itself double the size of its rivals.
As a designer what impressed me most about the early RS/6000 was its production engineering - the chassis and system level hardware was carefully engineered for lowest cost mass production, yet the CPU chipset was the most powerful and physically largest in the market made with the most expensive processes of the day. The floating power hardware in the chipset was intimidating to competing vendors.
IBM were anything but religious in their interpretation of 'RISC' and used around 100 instruction types in the architecture, including many powerful floating point instructions.
Using a mix of hardwired and microcoded control, the POWER architecture stretched the RISC definition to the limit.
The success of the POWER architecture in the RS/6000 was in the benchmark wars - marketing to customers was another issue in a deeply parochial market which saw little attraction in IBM's home grown AIX `Unix-like' operating system - did not go unnoticed. Motorola were smarting from Sun's decision to bail out from the 68KB series, and their new 88,000 series RISC engine was not proving to be a hot seller. Apple, until then wedded like Sun to the 68KB, saw a future world dominated by proprietary and often inaccessible RISC architectures.
Like IBM they needed a technology to compete with, and this led them to partner with IBM to develop the PowerPC RISC architecture.
The PowerPC architecture was a derivative of the IBM POWER architecture, but optimised for single chip, superscalar, multiprocessing and 64-bit implementations and utilising Motorola's experience in 88,000 series RISC processor bus. The first production PowerPC chip, the 601 used in entry level NuBus and PCI PowerMacs, excluded a number of IBM POWER instructions such as three integer rotate-insert, Load String and Compare Byte. The revised memory architecture saw the demise of a number of IBM POWER features. In summary, the PowerPC was a simplified and streamlined evolution of IBM's original architectural definition, accommodating a 64-bit model from the outset.
IBM developed their POWER series through the POWER2 (1993 - 1998), the 64-bit POWER3 (1998 on) and dual CPU POWER4 dies, focussing on their core business of 'Unixy' AIX workstations and servers. Apple and Motorola pursued the `lower end' of this architectural domain with PowerPC single chip implementations, with Apple populating their PowerMac motherboards and Motorola developing a thriving VME-bus product line for embedded applications.
The first generation of NuBus based PowerMacs with PPC 601 CPUs hit the market in 1994, and were superseded in 1995 by second generation PCI motherboards using the PPC 601, 603e, 604 and 604e CPUs - these remained in production until 1997.
The first of the third generation motherboards emerged in 1997, using a PPC 750 chip, but was soon superseded by AGP/PCI capable motherboards with the PPC 7400 (350 to 500 MHz / 10.5 million transistors) and later PPC 7450/7455 chips. These were known by the marketing name of 'G3' and 'G4' - the G4 including Motorola's 'Altivec' SIMD hardware labelled the 'VelocityEngine' by Apple and loudly advertised as a 'Cray on a Chip'. While the Altivec is a very nice short vector processing engine, one has got to wonder about the marketeers who opted to compare a 16/8/4 deep vector engine with a 64 deep Cray!
The new IBM 970 chip has a its roots in the IBM side of the POWER/PowerPC family, and presents an interesting transition in Apple's technology base - the G4 series chips were essentially G3 cores with the Altivec SIMD engine attached and were never competitive in t
Issue: 133 | February, 2012