Ever since Wesley Crusher discovered he could store all his hardcore Deanna Troi porn on a single optic chip, geeks everywhere have dreamed of viable holo-storage. Dr Carlo Kopp explores the niftiness of persistent memory and holographic bulk storage.
System storage, be it main memory, disk or tape, seldom attracts the visibility that developments in CPU and GPU technology produce. Nevertheless, the performance, cost and capabilities of main memory and bulk storage are critical to achieving high performance in a system, be it a fanatical gamer's desktop or a large server.
Existing DRAM technology is what can be termed 'non-persistent' or 'volatile' in that removing the electrical power driving the DRAM results in complete loss of the stored data. This is an inherent result of the circuit technique and device technology used. With DRAM each bit of data is typically stored as electrical charge in a capacitor -- usually implemented with a CMOS or NMOS transistor. That charge leaks out relatively quickly, so modern DRAMs include 'refresh logic' circuits which periodically read the contents of each bit in the DRAM and 'refresh' it by topping up the charge if the device needs it.
Volatility in DRAM technology is a nuisance we have learned to live with, and with a crap-house operating system or application producing frequent BSODs or 'bus errors' this is a nuisance most users can do without. Of bigger concern for many today is life in a world of deregulated electricity suppliers, who often provide mains power with daily dips, brownouts, glitches and dropouts. While an uninterruptable power supply (UPS) is a viable fix, it is an expensive fix and not as widely used as one might suspect.
Users of laptops and notebooks also have to deal with the realities of intermittent operation, and the standby modes in most such devices still result in appreciable power drain. While battery technology has improved remarkably in recent years, the laptop or notebook user will often end up with a beeping system, and their work vaporised before they can save it. Must users continue to live with the impediments of volatile main memory?
During the 1960s and early 1970s the dominant technology for main memories was based on magnetic cores rather than solid state transistors. Magnetic core memories were genuinely non-volatile or persistent. Remove the power and whatever was last stored in the memory remained in the memory until the system was powered up again and one or another application, such as a booting operating system, overwrote it. Magnetic core memories were small, slow and expensive and in today's world represent mostly a curiosity -- although some of these museum pieces have remained in operation in some obsolescent military equipment.
There is an anecdote, the veracity of which is unclear, which claims the core memories from the mission computers in the ill-fated Space Shuttle Challenger were fished out of the water, cleaned, hooked up into a testbed, and read out to establish what the computers believed was happening during the final milliseconds of the vehicle's life.
Until recently there have been only two robust non-volatile memory technologies, the FLASH and EEPROM (Electrically Erasable Programmable Read Only Memory) which has been widely used for storing configuration data in computer boards, but also mobile phones, microwaves and other consumer products. The limitation of FLASH/EEPROM technology has been in its slow write cycle -- even if it is competitive in read access times, it is slow to write. This asymmetry in timing, a propensity to wear out after a number of writes and cost make it nonviable as a candidate for a non-volatile DRAM replacement.
More recently chip designers and device physicists have made significant progress with three technologies, all of which are candidates for a full speed non-volatile main memory array. The stakes in this game are not trivial as DRAM and FLASH typically occupy a US$20 billion annual market segment.
Ferro-Electric Random Access MemoryThe FRAM (Ferro-Electric Random Access Memory) has been produced and marketed by Ramtron International in Colorado since the early 1990s, but until recently the density of these devices has relegated them to specialised low volume uses.
FRAM, like DRAM, uses a capacitor structure to store a '1' or '0' but unlike DRAM, which uses a conventional Silicon dioxide capacitor fabricated on the die, the FRAM uses a capacitor with a ferro-electric crystal material.
Ferro-electric materials, such as Lead-Zirconium-Titanate (PZT) have the interesting ability to hold an electrical charge indefinitely. The mechanism via which this occurs is in the crystalline lattice itself, as a central atom within the lattice can flip its position when an electric field is applied. If a capacitor is fabricated using a ferro-electric material as the dielectric then this capacitor will retain the electrical orientation resulting from the polarity of the electrical charge applied. The result of this is a mechanism via which a non-volatile memory cell can be produced as the capacitor retains its induced polarity even after power is removed.
When a ferro-electric cell is read, an electric field is applied. A current pulse results and its size will depend on the orientation of the stored state of the ferro-electric cell. If the atoms have to flip orientation a large pulse is produced, if they do not a small pulse is produced, and this is used to sense a '1' or a '0'. The read operation wipes the stored information in the cell, and therefore a refresh circuit is used to write it back into the cell.
Fabricating an FRAM is much trickier than fabricating a conventional DRAM, the Silicon die with the read/write and addressing circuits must have a layer of ferro-electric material applied to it, and this material has to be etched differently from the die material to produce the individual bit level memory cells. An advantage of FRAM technology is that it can be applied to portions of 'conventional' chips such as microprocessors or signal processors, and is likely to become a feature of many future embedded processors.
Until recently FRAMs were fabricated with 0.5 micron technology, and this did not produce a product competitive with DRAM chips. The best reported size for an FRAM was been a 64-megabit (8MB) device fabricated by Texas Instruments using 0.13 micron technology.
Ovonic Unified MemoryOvonic memory technology has a history even older than the FRAM, and was first proposed by Stanford Ovshinky during the 1960s. The mechanism it uses is quite different from the FRAM, and shares more in common with rewritable CD/DVD technology. The alloy used in current Ovonic memories was originally developed for the CD/DVD market.
Ovonic memories make use of alloys termed chalcogenides that can very quickly change between a crystalline and amorphous state when heated. What is important is that the chalcogenide has quite different electrical behaviour in either the crystalline or amorphous state -- when crystalline it has low electrical resistance, when amorphous it has typically 100-fold higher resistance. Therefore the crystalline or amorphous state of an Ovonic memory cell is used to store eith
Issue: 137 | June, 2012