Wednesday May 23, 2012 4:18 PM AEST

Atomic assembly - X-Ray #36

By Staff Writers
00:00 Apr 29, 2004
Tags: Atomic | assembly | | X-Ray | #36

90 nanometres is small, damn small. John Gillooly is big, and so are the challenges faced as semiconductors keep shrinking.

Click here to view the full page technical illustration for this article.

Like sands through the hourglass, silicon process technology is moving forward at a steady rate. Every year or so we see talk made of some company or another moving to smaller and smaller processes, with Intel now producing CPUs at 90 nanometres and other semiconductor manufacturers preparing to follow suit.

It is a steady march that has been occurring for almost half a decade now, as new process technology needs to be found to keep the transistor doubling predictions of Moores Law ticking away. For a while there it seemed liked manufacturers would smoothly transition processes every year or two, but as process technology approaches the atomic level more and more obstacles need to be overcome in fabrication and design.

We saw this in the transition of companies to 0.13 micron fabrication last year. While Intel managed to get it right early on with the 0.13 micron Northwood core for the Pentium 4, others did not enjoy as smooth a transition. AMD's first 0.13 thoroughbred Athlon XP CPUs ran hotter than John Howard in a thong bikini, and NVIDIA's earsplitting cooling solution for its heat pumping GeForce FX 5800 Ultra has become a thing of geek legend.

As companies now look towards 90 nanometre processes the issues just become magnified, and it is taking some tricky new technology to keep semiconductors running smoothly when constructed so finely. To understand how and why these new techniques work, you need a basic idea of how semiconductors are made.


Silicon rocks
Silicon is an amazing chemical element. It makes up 27.7% of the weight of the earth's crust and its properties have been utilised for some of humanity's most important technological advances.

The silicon used to make semiconductors starts out as quartz sand. However, the silicon used in chip making needs to have a pure crystalline structure, in which each of the four bonds on the silicon atom join to neighbouring atoms to form a pure silicon lattice.

To create the pure silicon wafers that form the foundation for semiconductors this lattice must be created. To do this, a rod with a silicon crystal - called a 'seed crystal' - is placed into a solution of molten silicon. This seed crystal is then slowly drawn out of the silicon in a process called 'seed pulling', which forms a giant silicon crystal, called an ingot.

This large, heavy, silicon ingot is then sliced, ground and polished into thin cross-sections called wafers. However because silicon is a semiconductor, and cannot natively carry a charge, it sometimes needs one more step before transistors can be constructed on the wafer surface, a process called doping.


ABOVE: An image from IBM showing transistors on an SOI (Silicon On Insulator) wafer and the copper interconnects between them.
Dope dealing
If we hark back to basic chemistry, you may remember that for a compound to conduct electricity it needs available bonds for electrons to attach to. Because silicon's four charges bond perfectly in the lattice form it is a very poor conductor of electricity, which is beneficial because it allows the manufacturer to control the flow of electricity through the die thanks to the process called doping.

Doping involves the addition of new atoms to the silicon wafer in order to change its electrical properties. There are two types of doping. The first is called P-Doping and it involves impregnating the surface of the silicon wafer with atoms of Boron or Gallium. These elements have only three electrical bonds, so when they are introduced to the silicon it gains a net positive charge, hence the name P-Doping. It is this process that the wafer undergoes before the initial growth of silicon dioxide.

On the flipside is N-Doping. This involves the introduction of either phosphorous or arsenic to the wafer. These elements have five bonds, and so when they bond with the silicon lattice there is one bond that's left over, which gives the section of wafer a net negative charge.


ABOVE: An electon microscope image of a transistor from Intel's 90-nanometre process, using a strained silicon wafer.
ABOVE: An extreme close-up of the gate electrode/wafer interface. Each dot is a single atom, and the thin middle layer is the gate dielectric.
Laying the foundation
While modern semiconductors are complex beasts, the basics of fabrication are the same across varying structures and die sizes. Creation of a chip involves several layering processes to build and connect the various transistors needed to crunch that binary data.

The process starts with the thin silicon wafer that has been sliced from the ingot. Because of the nature of semiconductor manufacture larger wafers are more economical to work with, hence most advanced processes use wafers that are 300mm in diameter. Before work starts on the chip itself, the wafer is P-doped, giving the wafer a mild positive charge that will let current flow across transistors once the chip making process is finished.

To kick off the chip-birthing procedure the wafer has a layer of silicon dioxide grown upon it. This layer helps to pr
 
 
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Atomic Magazine

Issue: 137 | June, 2012

Atomic is a magazine aimed squarely at computer enthusiasts, gamers, and serious PC upgraders.

Every month we bring you the latest reviews of new technology and PC components, in depth features on everything from overclocking to console hacking, and gaming previews and interviews.
 
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