80 core processor announced at IDF

Developers see the future of the Terraflop server processor with 20MB of memory and frickkin’ silicon lasers.

Thought four cores split over two processors was beefy? Are you looking forward to Clovertown? You may not see this for several years, but it shows that the Intel developers are thinking much bigger than a few simple cores on a single processor. Needless to say, the whole thing's very experimental at the moment.

Intel announced plans to have an eighty (80) core CPU by 2010. It’s calling this project Terra-scale Computing, as the chip is expected to reach teraflop levels of power. It was unveiled at the Intel Developer Forum (IDF) today, the 27th of September. Each core will run at 3.1 GHz, and by our calculations, a single chip sporting 80 cores will use only 102 watts of power.

Memory bandwidth problems will be addressed by stacking a layer of memory directly underneath the processor array. Each core is layered above 256KB of SRAM each. The transport improvements are estimated to result in a trillion bytes per second, which equals 931 GB/s of memory bandwidth.

To address the monstrous I/O requirements of a chip like this, silicon photonics developments are being used in lieu of electrical connections. The laser connectors control light from the silicon level through a CMOS level, which is known as a hybrid silicon laser. As a demonstration at the IDF, an externally driven array of sample hybrid silicon lasers was fired at an infra-red camera which showed the beams being broken.

Intel has stated that the moves to smaller production processes enable this kind of technology, as they can capitalize on the decreases in both heat output and cost per transistor. It is destined for applications that Intel has described as mega data centres, such as the ones that power Google and YouTube.

At the consumer level, a variation of the prototype would be able to dedicate a thread to a processor. This should lead to fewer lockups during use, not to mention the potential advancement in parallel software that will be implemented between now and then.