Inside the PlayStation3

Is it a supercomputer? How about a PC replacement? Or even just a games console? Time for some answers.

On 23 March 2007, the PlayStation 3 finally reached Australian shores. It didn’t exactly wash up on the beaches of Bondi in a sleek brushed aluminium crate or parachute drop into the centre of Sydney via C-5 Galaxy, but it did get here by more mundane, and slightly less insane, means.

The fact remains however that despite its technological ferocity, the PS3 is late. We went from a guaranteed global launch in November 2006 to a US/Japan only release with Europe, Australia and New Zealand shoved into the scary unknown of 2007. The more desperate PAL gamers who had banked on satiating their need for Sony’s high-tech games machine in November may have turned to eBay and shelled out exorbitant amounts of cash for an NTSC PS3. Others may have simply cradled their PS2 and wept silent tears until the crushing sadness abated.

A few just accepted the fact that products get delayed, and went out and bought an Xbox 360 or Wii instead.

Whatever your disposition towards Sony or the PS3, it cannot be denied that the console is a very different piece of hardware to the systems that have come before it, including Microsoft and Nintendo’s latest offerings. The PS3 is the embodiment of seven years of research into making computers better; facing and overcoming significant technological hurdles others have simply shrugged their shoulders at and a persistence to deliver to the industry a device with its feet planted, for the most part, in the future.

CELL DIVISION
Of all the components in the PS3, it is the Cell microprocessor that has received the lion’s share of attention, and rightly so. The joint project by Sony, Toshiba and IBM (STI for short) represents a fundamental change in the way a general-purpose processor should work, a change we’re only just starting to see in the consumer desktop space with the release of multi-core CPUs from Intel and AMD.

Cell started life as a series of discussions in 2000 and 2001, with IBM providing the know-how and Toshiba the facilities to produce the hardware. Sony wanted a chip that would outperform the PS2’s Emotion Engine by 1000 times. IBM, perhaps the realist in the situation, proposed a 100-fold increase in performance and an architecture that would scale for several years. Other goals decided on in this initial phase included a processor tuned for games and multimedia, responsiveness and platform androgyny. Oh, and it had to be really, really powerful. Like kick-arse powerful.

From the start Cell was always going to be a multi-core chip. Manufacturers like Intel had begun to realise that piling on the megahertz was no longer an effective strategy. Hitting this wall in the mid to late game would have meant certain disaster for the project. Cell needed to do much, much more work per clock cycle than other CPUs of the era.

‘I think that the period of time where microprocessor manufacturers can just keep increasing clock frequency to get performance improvements has reached the point of diminishing returns,’ says Bruce D’Amora, digital media solutions architect at IBM’s T.J. Watson Research Center in New York. ‘Multi-core processor architectures that efficiently support multithreaded application development are the future.’



The focus on gaming and multimedia meant it was unnecessary for every processing core on the new chip to include general-purpose registers and commands. The design could get away with the a single ‘standard’ processor to handle normal system demands and administrate, while the rest would be dedicated and highly parallel. This didn’t mean the sub-processors would be incapable of handling general purpose jobs, just that they wouldn’t be very good at it.

Cell also had to allow for high-bandwidth, low-latency memory transactions between the host and supplementary cores. How fast the cores could figure things out would be irrelevant if the memory input/output system was unable to efficiently feed them.

STI tackled this problem in two ways. The first was to give each supplementary core its own ‘local store’ that would supply both high-speed caching and data storage facilities. The second was to give each sub core a pair of one-way (read/write), asynchronous direct memory access (DMA) links to the data bus, connecting each with the host core and system RAM through the memory controller. In addition, each supplementary core would have a dedicated channel for communicating with the memory controller.

With an overall design in mind, STI glued together the following hardware to produce the final product.