Friday February 10, 2012 3:48 PM AEST

History of Overclocking Part Two

By Craig Simms
12:22 May 25, 2007
Tags: History | Overclocking | pentium | core2 | athlon | xp | mp | axia | cyrix | K6
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History of Overclocking Part Two
Legal fun
AMD’s move from Intel’s second-source supplier to standalone chip design firm is an interesting one – it all came to a head during the 486 years, when lawsuits arose and the chip hit the fan.

In June of 1992 AMD was told that it did not have a license for its 80287, an FPU based off Intel’s design. As Intel had incorporated its FPU into its 486 CPU, this presented a problem for future development.

AMD had a license granted for the 386 code, and so it seemed the only way it could progress to the 486 was to simply use the technology on which it had a license and extend it. April 1993 rolled around and in yet another court battle it was decided that AMD did have a license for the 80287, and wallah! The AM486, with microcode from the i486, appeared on the market.

4 June came and another decision was reached – AMD didn’t have a 386 license. AMD started to develop its own 486 microcode, although later evidence uncovered high percentages of i386 code.

On 30 December 1994, the Supreme Court of California denied AMD’s right to use Intel microcode. Immediately after which Intel allowed AMD to use 287, 386 and 486 microcode. Suspect? Perhaps. Intel had its new Pentium weapon to deploy, and AMD had decided to separate itself from the behemoth with its K5.

Celeron
(1998-2006, 0.25µm-65nm process, 266MHz-3.6GHz)

The original Celeron was a cut-down version of the Pentium II with no L2 cache, but it wasn’t until the ‘A’ revision, particularly the 300A, where overclocking hit with a boom. When it was introduced the Celeron received universal panning from the press due to its lack of cache and hence bad performance, and gave AMD some much needed attention and market share with its K6-2 chip.

The ‘A’ revision added 128KB of L2 cache back into the mix, but it ran at core speed as, unlike the Pentium Pro, was properly on-die. No longer limited by slow L2 times, overclocking improved massively with the 300A hitting 450MHz regularly when switched to a 100MHz bus from its default 66MHz.

By the time of the A revision, Celerons were circulated in both Slot 1 and Socket 370 form. As the cache was on-die, there was no need for the slot form factor, and the SECC cartridge was discontinued in 1999. The Celeron line continued to be cache-cut versions of Intel’s higher performing chips until the Pentium D was released in 2005, where it was sold single instead of dual core.

Also introduced was the slotket – a circuit board that could be plugged into a Slot 1 board so it could support Socket 370 chips. This came about due to lengthy delays in getting the Socket 370 standard to market.

In 1998 a program was released called SoftFSB by H.Oda!. SoftFSB allowed the PLL controlling the FSB to be manipulated directly through Windows, essentially allowing FSB tweaking on the fly. This was especially useful for those who didn’t have FSB tweaking options in their BIOS, however it came at a price – no ability to set AGP and PCI ratios. As both buses were divided from the FSB, any FSB increase meant that these went faster, leading to potential crashes. There would be many software programs like this over the years. The one enjoying the most popularity today is called SetFSB – as usual though, only limited PLLs are supported.

K6-2, K6-III
(1998-2000, 0.25µm-0.18µm process, 266-550MHz)

K6-2 was AMD’s answer to the Pentium II, although once again a little late. 3DNow! was introduced – a SIMD set that increased the performance of 3D applications to make up for the weak FPU. It became a popular alternative to the early cacheless Celeron, and remained popular in the face of the cache-enabled Celeron due to excellent price/performance. At this stage the K6-2 still relied on slower motherboard-based L2.

Intel’s insane Pentium II prices and first Celeron SNAFU led to AMD gaining significant market share and mind space with the K6-2.
Intel’s insane Pentium II prices and first Celeron SNAFU led to AMD gaining significant market share and mind space with the K6-2.


The K6-III came along in 1999, offering a 256KB on-chip L2 cache, and the motherboard mounted cache became L3. Upon its release, the K6-III was the fastest desktop CPU – something AMD would get used to in the coming years. Intel quickly put the Pentium III to market, a refined Pentium II architecture that allowed for higher clock speeds.

Pentium III
(1999-2003, 0.25µm-0.13µm process, 450-1000MHz)

The Pentium III would be Intel’s last solid hold on the market until Core 2 Duo. With it was introduced the first edition of Streaming SIMD Extensions, or SSE. To this day, SSE versions remain one of Intel’s strongholds, AMD usually only gaining compatibility a revision later.

Certain 450MHz SECC2-slotted PIIIs could hit 600MHz without breaking a sweat, the new cartridge allowing the CPU to have direct contact with the heatsink. The race for the gigahertz became real.

The ‘Coppermine’ revision was released, returning to socketed processors using a FC-PGA package for Socket 370. For the first time, people started caring about what kind of heatsink was fitted on their CPU, with companies like Globalwin, Alpha and Thermaltake coming to the fore. These were typically a pain to install, and were skull-crushingly loud to keep the CPU tamed at default speed, let alone overclocked. People began to talk about thermal interface material, and Arctic Silver became a household name. Cache was shifted on-die to compete with the K6-III and Athlons. As speeds ramped up to the GHz a third revision, ‘Tualatin’, was released.

Dividers and ratios began appearing to keep the PCI bus, AGP bus and RAM happy in the face of the different FSB speeds available (66, 100 and 133MHz).

Near the end of its life the Pentium III introduced what would be one of Intel’s worst decisions – RDRAM. While offering double-pumped frequencies (like DDR) and dual channel architecture (effectively doubling data throughput by teaming two 64-bit data channels to create a 128-bit bus – this would later be expanded to quad channel), RDRAM was hideously expensive, suffered latency problems, and Intel’s agreement with Rambus meant that its platform would use it exclusively – turning people to the AMD SDRAM/DDR alternative. It also signalled a return to the bad old days of populating all slots, with RIMMs needing to be paired, and every RIMM slot needing to be filled – a passive device known as a continuity RIMM had to be installed in the empty slots to make things work.

Over the years Rambus generated a lot of bad press, and eventually Intel separated itself from RDRAM in the latter half of 2003. This would be the first admission of many that AMD was on to a good thing.


 
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This article appeared in the June, 2007 issue of Atomic.

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Issue: 133 | February, 2012

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