Intel shows cache-quadding technology

Big arrays all round from the VLSI Symposium.

There's a geek-fest taking place in Hawai’i, of all places, and it’s called the VLSI Symposia – that’s fine by us, give us a working vacation any day over... um... just plain work. The crammed brains-in-attendance have been able to show some interesting developments in the field of semiconductor research – including Intel’s own slideware, which they’ve so graciously sent us for analysis.

If you’ve been following Intel’s achievements over the past few years, you’ll have noticed that Chipzilla is repeatedly reaching the design limit on a few elements in its chips. The latest example had been the leaky 45nm process, which Intel bathed in Hafnium and gave high-K metal gates. Now Intel is trying to push the cache to a guesstimated three to four times its current capacity by using Floating Body Cells (FBC).

Floating Body Cells have nothing to do with corpses bobbing up and down in the local canal. It’s all about SOI, and although Intel didn’t like IBM/AMD’s SOI back in the day, the chipmaker likes it enough now that it needs it. The FBC (your bit of storage) hangs under the gate and over the 10nm thin buried oxide (BOX) layer, meaning it's small, simple (read: cost effective) and – from what we garner – won’t suffer from the electric shortcomings of current DRAM designs. Intel also says it’s a bit more scalable than previous caches. This would also, potentially, lead to a new species of DRAM some time down the line, but Intel’s business isn’t about building DRAM, it’s about building CPUs.

Intel is plugging this as the next-gen of cache, with lower costs and higher density. The technology itself has been discussed and worked on by other companies for a few years now (the oldest we can remember was Toshiba presenting the same FBC tech, albeit with fewer refinements, at VLSI 2003).

One of the missionaries also presented (what we expect to be) the next transistor technology: High-K + Metal Gate strain-enhanced. Intel is counting on this tech to improve yields and shave some costs off CPU production – an all-round win-win situation, we guess.

Unfortunately the above technologies are still a work-in-progress, and Intel didn’t talk timelines – the slideware, however, does say that FBC is suitable for "15nm node and beyond" (about three to four years in our calendar) and High K+strained metal gate is the "best transistor results for any published 45nm or 32nm technology", which sounds like right about... uh... now? So you'd expect the Nehalem family to feature this tech as it launches.

For some reason (we can’t imagine why) the Intel missionaries tried to convert the native (and non-native) Hawaiians to the greatness of Nehalem’s clocks – on the argument that decoupling all the clocks and power settings (which for some reason *sounds* wrong to overclockers) is the way to go, hence Quick Path Interconnect.

Unfortunately they were all on Luau time and couldn’t care less.