Intel denies Core i7 TLB bug

And Nehalem was looking so rosy...

It seems Intel's new Core i7 chip may be a bit soggy on the translation lookaside buffer (TLB) front, with the firm hinting at a bug in an official Specification Update.

A TLB, found in pretty much all current desktop and server processors, is a CPU cache used by memory management hardware to improve the speed of virtual address translation.

Intel's spec update notes "In rare instances, improper TLB invalidation may result in unpredictable system behavior, such as system hangs or incorrect data". The document goes on to say "Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms. For the processors affected, Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue."

A TLB flaw could have serious implications for Intel’s street cred, but the firm insists there is nothing to get excited about. "This is a spec clarification that points back to a programmer's application note written by Intel in April 2007. The same spec clarification is in our Penryn docs pointing to same app note, which advises on programming techniques to avoid any issue", an Intel spokesman told us.

The Intel spinner went on to say that, as far as the spec clarification was concerned, the problem didn’t affect Core i7 or any Nehalem processor. "That was for Core 2 Duo and that has been fixed via BIOS updates long ago. Any outstanding software programmer developer manual changes are shown in all product spec updates so it was listed", he noted.

We've also been assured that if one were to look through the various Core i7 updates in the errata part of the spec update, there would be some mention of TLB (unrelated to the previous mention), but that anything significant had been fixed before Core i7’s launch.

Intel’s official Specification Update (page 37 AAJ1 Clarification)