VIA goes HyperTransport(ish)

Chipset giant VIA is the latest passenger on the HyperTransport wagon as it trundles towards the launch of AMD’s next generation Hammer chips. HyperTransport is being pushed by AMD as a chip interconnect solution, and will play an important part in

Chipset giant VIA is the latest passenger on the HyperTransport wagon as it trundles towards the launch of AMD's next generation Hammer chips. HyperTransport is being pushed by AMD as a chip interconnect solution, and will play an important part in how Hammer interfaces with the chipsets being developed for it.

So far the only real taste us consumers have had of HyperTransport has been in NVIDIA's nForce chipset, which uses HyperTransport for connection between the North (IGP) and South (MCP) Bridges. This is only one possible implementation of the technology, as it is positioned as a general chip interconnect technology rather than a specific means of communication between the component parts of the chipset.

In contrast VIA employs a competing technology called V-Link, which has been sped up in the VIA P4X333 chipset to double speed V-Link, providing an effective 533MHz connection between the North and South Bridges. So it begs the question of what future is there for V-Link now that VIA is part of the ever expanding HyperTransport consortium?

Rather than speculate we went straight to John Gatt at VIA and asked him what future V-Link has in both the Hammer chipsets and future chipsets for other processors.

Atomic: Does this mean that V-Link will die out once the chipsets for the current Athlon core are phased out?:
VIA: No it will not. HyperTransport is only part of the interface and we will have more than one chipset for the K8.

Atomic: Would you be employing HyperTransport in future generations of chipsets for Intel CPUs?
VIA: We have no plans to move from V-Link at this time for Intel or any other chipsets.

So, VIA is onboard the HyperTransport wagon, but will only be employing it in a limited role, with V-Link still having a future as an interconnect between the North and South Bridges. This leaves NVIDIA and ALI (ALI will be using rebadged AMD North Bridges and its own South Bridges for its Hammer chipset) using HyperTransport for internal communication within the chipset, with SiS' position still not clear.