Friday February 10, 2012 5:07 PM AEST

Nehalem has competition in some odd places

By The Inquirer
09:43 May 20, 2009 | 3 Comments
Tags: nehalem | core | 2 | quad | benchmarks
Nehalem has competition in some odd places

It's not AMD, it's not some weird server chip... it's an older Intel one!

No, it's not AMD, it's Core 2 Quad. Lotsa website gigglebytes were recently spent comparing the Phenom II Black Edition 955 to the Core i7 965 or the as still yet unannounced 975.

However, aside from extreme overclocking, Core i7 still wins almost all benchmarks. Same for its dual-headed twin, the Nehalem EP Xeon W5580. There is, however, some not so well advertised competition in some areas. Ever looked at the SiSoft Sandra 2009 AES cryptography benchmark? Here it is:

click to view full size image

Notice how the Nehalem is throughly overrun - by more than 10 per cent - by its immediate 3.2 GHz Penryn based predecessor despite the newbie running at 3.33 GHz in Turbo mode, while AMD needs to use 4-socket monsters to stay on the charts at least till Istanbul arrives? The same would apply on the desktop side, by extension.

Why? Well, every 'Yorkfield' Core 2 Quad or its 'Harpertown' Xeon equivalent have two dual core dies inside, each with 6 MB fast (15 to 18 cycle) L2 caches, for 12 MB total. Yes. there is a humongous FSB hop penalty when going between the dies, but it is still smaller than going between two chips across two FSBs and a North Bridge in between when using a DP system.

However, if for some reason your critical code fits nicely in that 12 MB cache, and the threads don't kiss each other too much over that FSB - and yet that same code finds Nehalem's shared 8 MB L3 at 35+ cycles depending on the uncore clock too small and/or slow - then that code may run faster on the older chip.

As mentioned before, I really hope that Westmere will have, besides a 12 MB L3 cache to feed its expected six cores, also an improved latency profile including eliminating the 3-cycle core-to-uncore penalty that exists right now even if both are clocked the same.

A 975X chipset-style PAT mode that cuts that latency for direct in-sync clock situations would be welcome back. In the meantime, if you have similarly clocked and configured 'Penryn' and 'Nehalem' generation systems, and time at hand, just play with your apps, you might discover some interesting stuff!

 

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3 Comments
fliptopia
May 20, 2009 2:30 PM
Is this an article to say that nehalem gets beaten in 1 synthetic benchmark?
Hawkeye
May 20, 2009 3:39 PM
In part, yes, but it also analyses what that might mean in a real world situation. It's more an interesting observation :)
robzy
May 22, 2009 12:50 AM
I think it was rather interesting to read about a fundamental part of microproccessor architecture.
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