Soitec and IBM go 3D

Layer upon layer of 22nm silicon...

Soitec is one of the movers and shakers at Semicon West this year, announcing it will collaborate with Big Blue to provide wafer thinning and bonding services to IBM. Soitec, the big daddy of silicon on insulator (SOI) substrates, is hedging its bets on next-generation 3D chip development with Big Blue at the 22nm semiconductor technology generation and below.

While still somewhat of a market niche, SOI has enjoyed success with IBM's chip division, and with AMD, over the past few years. But pundits expect the 22nm node to present challenges for SOI technology, and the use of 3D chip technology is one option to continue the push to scale down to smaller process sizes. This has to be good news for companies like AMD who rely on SOI for their CPUs, although one has to wonder how long until the firm moves to a bulk process considering Global Foundries will be able to offer littler chipper either one in the future.

3D chip technology doesn't lack for hype, and the boffins at IBM apparently see it as having huge potential to solve a number of problems which have been challenging chip designers hungry for more performance and less power at advanced process nodes.

3D chips layer one chip on top of another using a technique called wafer bonding, and this is where Soitec comes in. IBM's technique uses one base layer of silicon with active wafers layered on top. This allows engineers to place a processor on the bottom of the stack and then layer memory or other components across the top, resulting in a thousand-fold decrease in connector length, as chips are no longer organised in 2D layouts with wires connecting transistors at the outer layers of the chips. This reduces the distance data has to travel, resulting in much faster processing capabilities.

But how fast this technology will make it to market still remains to be seen.