Scientists help predict nanotech chip design

Atomic scale chip design.

Scientists at the University of Glasgow have developed a way of helping chipmakers create more reliable nano-circuitry.

Working with teams at the Universities of Manchester, Southampton, York and Edinburgh, as well chip companies like ARM and Wolfson Electronics, Freescale, National Semiconductor and Fujitsu, the researchers have created a set of simulation tools to help predict how billions of nano-transistors, each with its own unique and unpredictable atomic-scale variations, will perform in a circuit.

The study forms part of a £5.3 million Engineering and Physical Sciences Research Council (EPSRC) Escience pilot project called NanoCMOS.

Transistors today have gate lengths of 40nm or less and the smaller they become the more atomic-scale imperfections and variations - caused by the random number and position of discrete dopants - within each transistor become a problem

The simulations use grid computing to help tackle the problem of this statistical variability within the transistors that remains as a major obstacle to the large scale creation of nano-scale CMOS microchips.

"Since their invention in 1947, [transistors] have been getting smaller and smaller so that today we can place billions of transistors onto one small sliver of silicon," said Professor Asen Asenov, the principal investigator of NanoCMOS and leader of the device modelling team.

"If we are to continue to shrink the size of transistors in order to develop ever more powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the statistical variability."

According to Asenov, the days of 'happy scaling' in line with Moore's Law are over, however these developments should help chip designers to design reliable chips out of variable and unreliable transistors.

Using grid computing technology to distribute the workload, the team can create 3D numerical simulations of huge numbers of microscopically different nano-transistors, enabling them to accurately predict how they perform together.

"The NanoCMOS project has helped not only to understand, for the first time, intimate details of statistical variability, but also to develop enhanced algorithms that will allow accurate prediction of statistical variability with greatly reduced computational efforts," added Asenov.

"This will be a great benefit, not only to the major semiconductor manufacturers around the world, but also to the vibrant UK chip design industry that is facing the increasing challenges of the modern nano-CMOS technology and design."

The team is set to present results of its work at the International Electron Devices Meeting in Baltimore later this month.